LoRa RFM69

@gtmize I found the datasheet for the raw chip and have done a screen grab of the Version Register. See attached pics. I am also including ALL the code for the Lora Class begin function. As you will see there are only 2 returns in the code, one returns 0 on failure the other returns 1. The sketch code negates the return value so that success is now 0 therfore the if is NOT taken, and failure is now 1 or true so the if is taken and prints the error msg you are seeing. The datasheet I found is fairly easy to understand with regards to the Version Register. It MUST be 0x12.  It may be (my guess) that if the SPI bus was NOT properly wired and started then the readRegister might fail and give the appearance of an invalid version. In the previous post I gave you info on common SPI wiring and code errors that MIGHT cause this.

My suspicion is that the (illegal w/o special license) 433 chips are NOT Ver 0x12. If you are getting this error on 915MHz chips, then they are most likely not legit chips.

FYI: The #if defined is NOT your board so is not included.

int LoRaClass::begin(long frequency)
{
#if defined(ARDUINO_SAMD_MKRWAN1300) || defined(ARDUINO_SAMD_MKRWAN1310)
  pinMode(LORA_IRQ_DUMB, OUTPUT);
  digitalWrite(LORA_IRQ_DUMB, LOW);

  // Hardware reset
  pinMode(LORA_BOOT0, OUTPUT);
  digitalWrite(LORA_BOOT0, LOW);

  pinMode(LORA_RESET, OUTPUT);
  digitalWrite(LORA_RESET, HIGH);
  delay(200);
  digitalWrite(LORA_RESET, LOW);
  delay(200);
  digitalWrite(LORA_RESET, HIGH);
  delay(50);
#endif

  // setup pins
  pinMode(_ss, OUTPUT);
  // set SS high
  digitalWrite(_ss, HIGH);

  if (_reset != -1) {
    pinMode(_reset, OUTPUT);

    // perform reset
    digitalWrite(_reset, LOW);
    delay(10);
    digitalWrite(_reset, HIGH);
    delay(10);
  }

  // start SPI
  _spi->begin();

  // check version
  uint8_t version = readRegister(REG_VERSION);
  if (version != 0x12) {
    return 0;
  }

  // put in sleep mode
  sleep();

  // set frequency
  setFrequency(frequency);

  // set base addresses
  writeRegister(REG_FIFO_TX_BASE_ADDR, 0);
  writeRegister(REG_FIFO_RX_BASE_ADDR, 0);

  // set LNA boost
  writeRegister(REG_LNA, readRegister(REG_LNA) | 0x03);

  // set auto AGC
  writeRegister(REG_MODEM_CONFIG_3, 0x04);

  // set output power to 17 dBm
  setTxPower(17);

  // put in standby mode
  idle();

  return 1;
}