IIRC, ALL GPIO pins on the GIGA are available for interrupts BUT I have not seen enough documentation yet to determine if like other Arduino boards that there are x pins per PORT. If for instance there are 3 pins per port, then the number of independent interrupts is (76GPIO - 16special) / 3 equals 20 discrete interrupts.

Of course you have to decide between External interrupts and Pin Change interrupts (see below) but with at least 20 discrete interrupts to work with it is hard to see someone running out of them.

The major difference between INTx external interrupts & PCINT is that PCINT interrupts are grouped into 3 interrupt signals one for each port. If any pin in any port has changed state, the whole port is suspected to have changed.

I hope that helps to clarify interrupts a bit more.

I tried to find the documentation I saw a couple days ago with a lot of detailed info but couldn't. If I do find it I will post back here with the link.

If we remind ourselves what an NMI is and why we 'need' it, it's simply the highest (what if more than 1) priority interrupt and to answer the second part of the self question, it's needed in case an unknowing coder forgets or does not know about an interrupt that is of the highest priority. Since we are talking about MPU/MCU devices, there is almost always only a single programmer as opposed to a team of many so by definition we know about that highest priority as we are designing and implementing the application.

I suspect that what the OP was really asking is if there are pins on the Giga Display that can be used as an interrupt for some purpose like maybe vblank interval in order to update some critical portion of the screen. I am too lazy right bow to go refresh my memory, but my hunch is YES.

  You are probably right in saying there is not an NMI option.

  But if an interrupt is set to 'top priority', and the programmer does not disable all interrupts, then I suggest it should approximate to the same thing, albeit I have never tried this scenario. The implication being that if a piece of code needs protecting from interrupts, excluding the 'top priority' one, then the interrupt priority system is invoked.

Of course, this requires the programmer to cooperate, whilst the original NMI pin was always active. The upside is that a pin is not 'wasted' for applications that did not have a use for the NMI capability.

Sorry, but I don't know how easy and convenient using the priority system is in practice. I suggest the total 'convenience' assessment may depend on the application's reason for needing an NMI capability, and the circuitry being used to drive the NMI input to the microcontroller.

I regard this as the type of question that needs some preliminary 'feasibility' R&D, when considering an application that appears to need an NMI style capability.

And sorry Ron, but I can't help you with suggestions for a good reason for buying a Giga board with a display ... but ponder on it for a day or three ... something may occur to you. 😎 

Best wishes, Dave

Re NMI query

It is a long time since I saw NMI as a topic of conversation ...

 I am not familiar with the Arduino Giga, nor the processor at its heart, but a quick Google said it was based on the STM32H747XIH6, and the data sheet for the group of devices that that one is a member of, headlines with "Up to 168 I/O ports with interrupt capability".

Because modern processors usually have a large number of possible interrupt sources, they have to include some hardware to prioritise and mask multiple interrupts on a preconfigured control basis. This means you can effectively preset any one of a considerable number of pins to behave rather like a dedicated NMI pin, and hence there is no need to dedicate a specific pin to the role, when designing the chip.

Of course, it may also imply a fair bit of manual reading, etc. to figure out how to programme it to do a task that previously only requiring wiring to the pin labelled NMI 🙄 

So, whilst it is basically still a hardware function at 'run time', I expect it to require at least a little software in the 'boot' section to achieve the result.

As I say, I have only glanced at the datasheet, but I have described the general story I have seen in other processors in the more recent past. I hope it is at least 'roughly' correct.

Best wishes, Dave